Abstract
Estimating the power consumption and computational complexity of various digital signal processing (DSP) algorithms used in wireless communications systems is critical to assess the feasibility of implementing such algorithms in hardware, and for designing energy-constrained communications systems. Therefore, this paper presents a novel approach, based on practical system measurements using field programmable gate array (FPGA) and application-specific integrated circuit (ASIC), to evaluate the power consumption and the associated computational complexity of the most common mathematical operations performed within various DSP algorithms. Using the proposed approach, a new metric is developed for mapping the computational complexity to the computational power consumed by the mathematical operation in wireless transceivers. This allows combining the commonly used computational complexity metrics that are typically computed for each mathematical operation separately. Consequently, a single unified metric can be used to describe the entire algorithm. Therefore, the comparison and trade-offs between different algorithms become easier and more informative. The developed approach is used to evaluate the computational power of several DSP algorithms used in wireless communications systems, and perform thorough computational complexity comparisons. The obtained results reveal that computational complexity comparisons using different mathematical operations can be highly misleading in several scenarios. The power consumption evaluation of the considered DSP algorithms show that some algorithms may require a prohibitively high power, which makes such algorithms unsuitable for power-constrained wireless communications systems. The results also show that the proposed methodology can be adopted for various hardware implementation, however, some calibration might be required based on the adopted platform.
Highlights
MEASUREMENT RESULTS The measured power consumption of the considered arithmetic operations and the curve fitting results are presented in Figs. 4, 5 and 6, where the clock frequency is measured in MHz
The total computational power can be computed and presented into a single metric, which makes the comparison between different algorithms simpler and more informative
The results showed that the computational power for the considered arithmetic operations scales almost linearly with the number operations and frequencies, which enabled the construction of simple computational power models
Summary
E NHANCING the battery lifetime through power optimization is currently one of the critical challenges for several wireless communications systems. Examples for such applications include deviceto-device (D2D) communications [19], Wi-Fi [20], and the narrowband Internet of Things (NB-IoT) [21], [22]. E. ENERGY ANALYSIS By noting that all considered operations are base on combinational logic design, the energy consumed by each operation can be computed as the product of the measured power and maximum combinational path delay τ , the consumed energy can be expressed as E+ = τ+P+, E− = τ−P−, and E× = τ×P× for addition, subtraction and multiplication, respectively. The obtained results indicate that adding the powers of individual operations can be considered generally as an accurate indicator for the total power consumed by a certain of the algorithm
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