Computation of prime factor DFT and DHT/DCCT algorithms using cyclic and skew-cyclic bit-serial semisystolic IC convolvers

Abstract

The paper presents the results of a study of the use of cyclic and skew-cyclic convolvers for the evaluation of the subspace discrete Fourier transforms (DFT) and discrete Hartley transform (DHT) modules resulting from a prime factor decomposition of the DFT and the DHT/discrete cas-cas transform (DCCT), respectively. The method of Rader is employed to convert the subspace DFT/DHT modules into cyclic convolutions (CCs). These are further dissected into CCs and skew-cyclic convolutions (SCCs), respectively, of length ½(Ni − 1), where Ni is the DFT/DHT module length in the ith stage. That allows both real and complex DFT modules, as well as DHT modules, to be computed with the same convolver structure, by a simple reconfiguration of a recombination stage.This has important consequences for hardware implementations as only one type of convolver needs to be fabricated. A family of VLSI building block processors (BBPs) with pipelined bit-serial arithmetic is proposed. All inner products are computed in parallel within each BBP, resulting in a throughput rate inversely proportional to ½(Ni + 1). This leads to easy load balancing, which is discussed first in the context of a array machine and then in that of a multiplexed pipelined machine.