Abstract
In this paper, a technique to extend the linearity and to improve the efficiency of power amplifiers (PAs) is analyzed. The method avoids complex topologies, often affecting the radio-frequency performance and increasing the power consumption, chip area, and costs. In contrast, this approach can be implemented by a simple, but sophisticated design of the input biasing network. In this case, the input biasing network works in such a way that the dc current consumption adapts inherently to the demanded output power while ensuring high linearity. The large-signal behavior is analyzed, and analytical equations for the optimum parameter of the bias network are derived. For integration reason, the network is extended to a compact solution, which also includes the source resistance. According to these theoretical considerations, a PA is implemented in a 0.25- $ {\mu }\text{m}$ SiGe BiCMOS process. The analytical solutions are verified by the measured output-referred 1-dB compression point of 23.6 dBm. To estimate the improvement by using optimum values of the elements, simulations reveal an increase of the input-referred compression point by 2 dB and by 7% of power-added efficiency.
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