Comprehensive study on the performance comparison of logically reversible and irreversible parity generator and checker designs using two-dimensional two-dot one-electron QCA

Abstract

The limitations of CMOS technology led to the discoveries of new technologies, one of which is quantum-dot cellular automata. This upcoming technology is making its way because of high efficiency, high speed and small space requirement. Two-dot one-electron cells are used to design a parity generator and checker. Parity generator and checker aids in flawless binary data transmission from the source to the destination. Both irreversible as well as reversible parity generators and checkers are designed. It is seen that the amount of energy and power needed to drive these architectures is very low.