Comprehensive study of the features, execution steps and microarchitecture of the superscalar processors

Abstract

The paper introduces the concept of Superscalar processors; with details about the unique features which help achieve the final goal of lesser execution time and increased speed with minimal of added complexity in the architecture. The paper begins with comparing the other types of processors like Vector and Scalar, and explains how Superscalars prove better ones and further it also excoriates the common misconception about Superpipelined and Superscalar methods of instruction execution. Adding on, the unique features of Superscalars, which are Out of Order execution of instructions, Register Renaming, etc. are explained with example. In addition to features, the basic six implementation steps are introduced, and three basic tasks of Superscalars are explained which include Parallel Decoding, Superscalar Instruction and Parallel Instruction. Further on, the Microarchitecture of Superscalars is explained. Here, the five hardware parts which are Instruction Fetch and Branch Prediction, Decode and Register dependence analysis, Issue and execution, Memory operation analysis and execution and Instruction reorder and committing state, are explained. [2] Thus, the paper provides a comprehensive study of all the features, implementation steps and microarchitecture of Superscalar processors, which are proving to have the fastest instruction execution speed in its class.