Abstract
In this paper, we propose a component-based approach to verify system-level designs. The coordination language Reo is selected as an Architecture Description Language (ADL) to model system designs written in SystemC. In our approach we map a SystemC design to a Reo circuit, and then construct the corresponding constraint automata which show the behavior of the system and can be used for analysis purposes. The elegance of our approach is in using Reo and constraint automata as a pair to capture the structure and the behavior of the system together. We checked the correctness of our approach by comparing the SystemC simulation kernel behavior with the behavior of the glue code we proposed.
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