Composite PFD based low-power, low noise, fast lock-in PLL

Abstract

It has been found that the proposed PLL design results in reduced lock time and reference spur while maintaining stable closed -loop operation. Composite PFD provides high gain and high loop band width (BW) during lock -in and lower loop BW after getting locked -in resulting in improvement in lock -in and noise characteristics. NL-PFD helps in eliminating blind zone, and linear PFD helps in eliminating dead zone while suppressing unwanted glitches completely from the output of the PFDs resulting in reduced reference spur. Charge pump and LF topology have been developed so as to maintain constant phase margin to ensure stability during tracking and after lock -in. A prototype of PLL operating at 2.56 GHz developed with 180 nm CMOS process is found to achieve reference spur of -71.4 dB c at 20 MHz offset.