Complex Monolithic Arrays: Some Aspects of Design and Fabrication

Abstract

Large scale integration is the simultaneous realization of large area circuit chips and optimum component packing density for the express purpose of reducing costs by maximizing the number of system connections done at the chip level. The highly complex monolithic circuits being offered today are obviously the forerunners of true LSI. Many questions pertinent to LSI are asked repeatedly today. Some of the more timely aspects of large scale integration are considered here. The prime objective of this paper is, therefore, to establish where LSI is today. The coverage is limited to bipolar silicon integrated circuits. A DTL design is compared to an ECL design to illustrate a basis for choice of circuit type, power level, and interrelationship with respect to resistor and transistor parameters. Arrays of DTL and ECL gates with single-layer interconnection metal are next considered; each gate is assumed to have one semiconductor crossunder tunnel. The resulting expressions relate the maximum allowable number of DTL and ECL gates in the monolayer array to circuit threshold. Next, the characteristics of metal interconnections are examined to obtain a method for predicting average interconnection length, die area occupied by the interconnections, and signal delay introduced by the interconnections. Finally, some thermal aspects of packaging a square hybrid LSI array of 2n X 2n chips are analyzed for an ECL and a DTL design. An expression is derived which relates power density of the hybrid array to the number of gates in the array and pertinent properties of the base system.