Abstract
The structure of a 32-channel system of asynchronous data processing is considered. The data come from the detectors of nuclear physics experiments. Processing is provided for signals with a mean frequency of up to 10 MHz in each channel. The system provides generation of data packages, consisting of digital codes of signal amplitude, of signal superposition in peak detectors, of signal arrival time and number of channel wherein the event has occurred with a subsequent 8b10b coding. The considered system allows us to regulate dynamically the number of active channels. Two interface of data exchange – the slow I2C and high-speed (320 MHz), providing communication IC with the GBTX chip, have been built in the system. The results of developing the structural diagram and circuital-layout solutions of separate units are presented. System prototyping is implemented by the 180nm CMOS technology of UMC. The results of testing both separate blocks and the whole system are presented.
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