Complete x-ray lithography processing of an 8-level 0.4 micron CMOS test device

Abstract

Sub-0.5 μm CMOS devices have been successfully fabricated by means of X-ray lithography at all levels. The overlay of subsequent lithography levels was determined to be ≤180 nm, 3 σ. A linewidth variation in the poly-Si gate level of ± 50 nm could be achieved. The applied CMOS process uses dual p+/n+ poly-Si gates, oxide sidewall spacers and Co-silicided junctions. NMOS and PMOS transistors exhibit no severe short channel effects for gate lengths down to 0.35 μm with a supply voltage of V D= 5 V. A stage delay time of 120 ps was measured at a 33 stage 0.45 μm CMOS ring oscillator.