Complete test-set generation for bridging faults in combinational-logic circuits

Abstract

The present paper describes some algorithms for generating complete test sets for bridging faults in combinational logic circuits. It is shown how the concept of Boolean difference, which is well understood in the case of stuck-type fault situations, can be employed to generate the complete test set for bridging faults in combinational networks. The cases of single bridging fault and multiple input bridging fault are dealt with. An algorithm is also described for generating the complete test set of a combinational logic circuit in which a single stuck-type fault occurs in the presence of a bridging fault.