Abstract
The first circuit results for a new GaAs complementary logic technology are presented. The technology allows for independently optimizable p- and nchannel transistors with junction gates. Excellent loaded gate delays of 179 ps at 1.2 V and 319 ps at 0.8 V have been demonstrated at low power supply voltages. A power-delay product of 8.9 fJ was obtained at 0.8 V.
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