Compiling an RT level hardware description language into layout of NMOS cells

Abstract

A Hardware Description Language at the Register Transfer Level (RTL) is used as the front end of a VLSI Design Automation system. The DA package includes several simulators and hardware compilation programs including a layout generation program. The layout program takes as input a library of cells consistant with the constructs of the hardware language. In this paper the DA package, cell library, and the compilation algorithm are described.