Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions

Abstract

This paper describes the development and compiler utilization of variable length instruction set extensions to an existing high-performance, 32-bit VLIW DSP processor. We describe how the instruction set extensions (1) reduce code size significantly, (2) are binary compatibile with older object code, (3) do not require the processor to switch "modes", and (4) are exploited by a compiler. We describe the compiler strategies that utilize the new instruction set extensions to reduced code size. When compiling our benchmark suite for best performance, we show that our compiler uses the variable length instructions to decreases code size by 11.5 percent, with no reduction in performance. We also show that our implementation allows a wider code size and performance tradeoff range than earlier versions of the architecture.