Compilation of Parallel Data Access for Vector Processor in Radio Base Stations

Abstract

The data size and data feature under the cur-rent mainstream compilation schemes can be diversified, formal methods are thus mandatory. However, in a micro base station, as an embedded system, the typical feature or opportunity of baseband algorithms is its predictable small code and data sizes. The research is thus needed and there is so far no dedicated research on the related register alloca-tion algorithms. In this letter, we focus on compilation re-search for baseband kernel subroutines of 5G micro base stations. We proposed a parallel data access compilation scheme for applications with fixed and known data size, while operation data can be mostly stored and allocated in register file. The goal of the compilation scheme is to opti-mize algorithms based on 4x4 or smaller matrices, to reach the maximum register file utility, and eliminate the extra register data swapping. At the same time, we hide the data access time when allocating data into register file, and minimize the data access cost by using VLIW machine, so that the overall running time is minimum. Based on a small register group (48x32b) and the proposed compilation method, this letter implemented frequently used baseband subroutines (kernels) of 4x4 matrix with complex variables of 16b+16b and reached minimized run time. Results show that the extra addressing and data accessing cost is mini-mized for algorithms with small data size.