Compensating trigger jitter and time interval error measurement for digital sampling oscilloscopes with hardware design on FPGA

Abstract

This paper presents the creation and realization of a precision time base (PTB) for mitigating jitter and measuring time interval error (TIE) in digital sampling oscilloscopes (DSO), achieved through the utilization of a field programmable gate array (FPGA). Our proposed method focuses on mitigating jitter through PTB, which involves the sampling of two reference channels having a phase shift of approximately 90∘ (at quadrature) for an accurate timebase correction. Through extensive experimentation and analysis, we were able to achieve a reduction in root mean square (RMS) jitter, minimizing it to around 260 fs. This outcome demonstrates the effectiveness of our approach in enhancing the accuracy and reliability of DSO measurements. Expanding on the application of our previously proposed technique, we demonstrate that the same sampling error correction approach can be utilized for TIE measurement. By sampling a large amount of data at either the rising or falling edge of a sinusoidal signal, TIE can be accurately evaluated. This extension enhances the versatility of our FPGA-based implementation by enabling comprehensive TIE analysis alongside PTB compensation in DSOs.