Abstract
Safety-critical systems have to ensure safe operation in the face of random hardware errors. To meet these re-silience requirements in embedded systems, Software Implemented Hardware Fault Tolerance (SIHFT) methods offer an attractive solution. Though SIHFT research is mature, porting such methods to a specific processor architecture poses a challenge. In this paper, we present our open-source COMPAS compiler framework that realizes state-of-the-art SIHFT error-detection approaches targeting RISC- V processors. SIHFT transformations for major instruction classes such as loads, stores, branches etc. are described in terms of RISC- V code. Furthermore, we perform RTL fault injection analysis to accurately quantify soft error resilience of RISC- V programs. The results demonstrate enhanced resilience of RISC-V software equipped with COMPAS transformations, in line with earlier SIHFT works.
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