Comparison of two-phase latch configurations for pipelined processors in MOS VLSI: case study: a CMOS systolic multiplier

Abstract

It is shown that for bit-level pipelined processors whose elements require no precharge phase, pipelining with master-slave latches gives a theoretical maximum throughput of nearly twice that of the Mead-Conway alternating phase arrangement. A comparison is made between area and power requirements as a function of clock rate, both in general terms and with reference to a design example; a pipelined multiplier implemented as a bit-level systolic array.