Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies

Abstract

The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40 nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.