Abstract

Silicon carbide (SiC) trench MOSFETs, or UMOSFETs, generally exhibit lower specific on-resistance than planar DMOSFETs due to a more compact unit cell, higher electron mobility on the a-face surface, and the absence of a JFET region. In this paper we compare the performance of two types of trench UMOSFETs based on 2-D SentaurusTM Device simulations, and show that the single-trench oxide-protected structure exhibits ~40% lower specific on-resistance and half the peak oxide field of the double-trench design when both are optimized for maximum figure of merit.

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