Comparison of shallow trench and LOCOS isolation for hot-carrier resistance

Abstract

Hot-carrier stresses were performed on n-MOS transistors with LOCOS and shallow trench isolation. For transistors stressed under the different damage creation conditions, no discernible difference in lifetimes was found for devices down to W/L=3/0.45 mu m. It is shown, however, that the edge of the trench isolation (0.1 mu m wide) is more sensitive to hot carrier effects, having a lifetime up to four times less than the center of the channel. For devices with a W/L ratio of two or less, this could prove problematic. It could also have repercussions for transistors under high-gate-field (Fowler-Nordheim) conditions. >