Comparison of product failure rate to the component soft error rates in a multi-core digital signal processor

Abstract

The paper presents an approach to characterize soft error rates (SER) for an advanced 0.13 /spl mu/m, multi-core, voice-over-packet digital signal processor (DSP) system in accelerated alpha-particle and neutron environments. In both cases, we observed a close correlation when we compared the SER data of the DSP product memory to the stand-alone SRAM test chip SER data. Our embedded memory SER data is independent of frequency and memory block size, indicating that cell SER is the dominant component of the memory SER. We highlight the importance of the logic SER contribution to the overall chip-level SER. We also discovered a strong data state dependence for latches in the alpha environment, but not in the neutron environment. This discovery illustrates the nature of charge collection processes in these two environments, and lays the foundation for modeling logic SER. We characterized the failure rate of the DSP as it ran a representative end user application, allowing validation of the standard component SER testing methods.