Abstract
In traditional development methods, design verification is time consuming and costly. In order to overcome this issue, it is required to perform verification at early stage of development. For this purpose, formal methods are widely used to verify the software and hardware design mathematically through different formalisms. Timed Automata (TA) is a renowned formalism commonly used for the verification of real time embedded systems. Verification of time related aspects adds addition complexity; therefore, it is always challenging to select right verification tool for timed automata formalism. This article presents a comprehensive investigation of two leading formal verification tools i.e. PRISM and UPPAAL using timed automata. Particularly, a benchmark case study is used to perform modeling and verification in both tools keeping in mind few evaluation parameters. The results reveal that UPPAAL is more flexible in terms of usability and easiness. On the other hand, PRISM provides good features for probabilistic models. Finally, it is analyzed that UPPAAL overall performs well.
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