Comparison of hardware and timing penalties for eliminating SRAM failures

Abstract

This article provides a quantitative estimation of timing and hardware penalties, which are the implication of different SRAM methods for failure elimination. Different ways of building fault-tolerant blocks of SRAM are discussed using error-correcting codes and self-testing – self-repair units. As criteria for evaluating hardware costs, the additional chip area required for the placement of fault tolerance is considered, the timing penalties are determined by the growth of memory access time. Comparative analysis of obtained results is made. It allows estimating the effectiveness of the considered methods of fault tolerance improvement.