Abstract
In the deep submicron regime, FinFET successfully suppresses the leakage current using a 3D fin-like channel substrate, which gets depleted and blocks possible leakage as the gate is applied with a bias wholly wrapping the channel. Fortunately, a scanning photo-lithography using extensive ultraviolet (EUV) and multi-mask task carefully resolves critical dimension issues. The ensuing anisotropic plasma dry etching is somehow a subsequent challenging process, which consumes the edge of original ‘I’-shape epitaxial silicon and causes dimension loss, and thus produces fin-like bodies as prepared channels. In order to protect the transistors from malfunction due to dimension over-etching, fin width is taken to be 120 nanometers, while the channel lengths vary. The prepared transistors are measured and characteristic curves are fitted for analysis. Measured current versus voltage characteristic curves are fitted with three parameters (transistor geometry constant, threshold voltage, and Early voltage) in the conventional current-voltage formula, which are allowed to vary as the short channel effects or process-related issues are taken into account. In this paper, one of the three is deliberately set to be fixed for a transistor, and the others are freely chosen and determined to reach minimum variation. Various conclusions through comparisons and analysis may give important feasible applications in the future.
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