Comparison of different multiplier algorithms and 1D-DWT as an application

Abstract

This paper compares 4 different multipliers and the one with the least area and power is applied in 1D-DWT. The multipliers are implemented using booth algorithms as well as Wallace tree structures. The advantage of using Modified Booth algorithm is that the number of partial products is reduced by half. The Wallace tree structure is used for partial product reduction. 1D-DWT is implemented using modified Wallace tree structures alone as it has the least area and power. The 1D-DWT is mainly used for image compression. Keywords - Modified Booth algorithm, Wallace trees, 1D-DWT. I. INTRODUCTION Multipliers form a major part of DSP applications. This paper focuses on different combinations of multipliers using Wallace trees and modified booth algorithm. The multipliers are used in 1D-DWT which is used for image compression and signal processing applications. Any multiplier design has 3 steps. They are i) partial product generation ii) partial product reduction iii) final addition. The partial products are formed first either by using modified booth algorithm or by ANDing each bit of the multiplier with each bit of the multiplicand. The next step is reduction of these partial products to two rows. This is done by grouping the partial products into groups of three. These groups are reduced by using carry save adders. Carry save adders are mainly full adders and half adders. The third step is addition of the final two rows by using carry look ahead adders to yield the final product. This paper focuses on 4 different combinations of multipliers. They are i) conventional Wallace trees ii) modified Wallace trees iii) modified booth- Wallace trees iv) modified booth- modified Wallace trees. They are compared in terms of area, power and delay. It is seen that modified Wallace tree has the least area and power. Hence the modified Wallace tree is used for 1D-DWT. The DWT is also used for signal processing applications. 1D-DWT uses low pass and high pass filters for signal analysis and reconstruction. The area , power and delay parameters are also found out using synopsys design compiler and Xilinx tools. The area and power are also listed in the tables in section IV.