Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node

Abstract

We report on particle induced upset rates of combinational and sequential logic. A novel test chip has been designed in a 32nm process to study the effects of single event transients (SET) and to verify the accuracy of our simulation models. The test chip has been tested under neutron and alpha particle radiation. Our measured data verify simulation-based projections that while static logic at the 32nm technology node is sensitive to both alpha particle and neutron radiation, it is not a dominant contributor at the chip-level.