Abstract
In this work the authors presented a field programmable gate array (FPGA) and a digital signal processor (DSP) implementations of an algorithm for real-time signal detection and denoising based on undecimated (stationary) wavelet packet transform (SWPT). The performance was compared in terms of operating clock frequencies, power consumption and signal-to-noise-ratio (SNR) due to finite word-length effects using a fixed-point arithmetics in the FPGA and floating-point in DSP. Finally the possibility of reconfiguration and extension is considered
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
