Abstract

Extracting gate-drain overlap oxide capacitance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oxd</sub> ) is a necessary step for almost all kinds of insulated-gate bipolar transistor (IGBT) compact models. There are two datasheet-driven methods that are universally accepted, one is based on reverse capacitance voltage characteristics ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C–V</i> method), and the other uses gate charge characteristics ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q–V</i> method). This letter is to reveal the underlying mechanism of these two methods. It is found that the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C–V</i> method has an inescapable shortcoming which will mistake the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> delay time forecasted by IGBT models. In this letter, the internal capacitance system of IGBT is modeled and demonstrated completely. Based on this model, the accuracy and feasibility of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C–V</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q–V</i> methods are analyzed. Moreover, the effect of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oxd</sub> on IGBT compact models is studied and further verified by experiments and circuit simulations.

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