Comparator design for linearized statistical flash A-to-D converter

Abstract

We proposed a linearization technique with dynamic element matching for stochastic flash A-to-D converters (SFADCs), and estimated that 6-bit SFADC can be realized by using about 1,000 comparators through system level simulations. In this paper, we present circuit level design of the linearized SFADC. First, we discuss the difference between requirements of comparators for conventional flash ADC and linearized SFADC. It was made clear that the offset voltage distribution for the comparators must have the same variance within a required linear input range for proper linearization. Based on the considerations, we designed a comparator for 6-bit resolution of a linearized SFADC with 1 GHz sampling by using a standard 0.18 pm CMOS process. The designed comparator has 15 pV sensitivity at 1 GHz sampling by simulation. Monte Carlo simulation of input offset voltage for the comparators indicated 63 mV standard deviation. We applied the linearization technique that 1,024 comparators are divided into 8 groups of 128 comparators. It achieved wide linear input range of 580 mV. The simulation results show 38 dB of spurious free dynamic range for 100 MHz 500 mVp-p input sine wave. This verifies the feasibility of 6-bit 1 GHz linearized SFADC.