Comparative study of electrical characteristics for n-type 4H–SiC planar and trench MOS capacitors annealed in ambient NO**Project supported by the National Basic Research Program of China (Grant No. 2015CB759600), the National Natural Science Foundation of China (Grant Nos. 61474113 and 61574140), the Beijing NOVA Program, China (Grant No. Z1611000049161132016071), China Academy of Engineering Physics (CAEP) Microsystem and THz Science and

Abstract

The interface properties and electrical characteristics of the n-type 4H–SiC planar and trench metal–oxide–semiconductor (MOS) capacitors are investigated by measuring the capacitance voltage and current voltage. The flat-band voltage and interface state density are evaluated by the quasi-static method. It is not effective on further improving the interface properties annealing at 1250°C in NO ambient for above 1 h due to the increasing interface shallow and fast states. These shallow states reduce the effective positive fixed charge density in the oxide. For the vertical MOS capacitors on the () and () faces, the interface state density can be reduced by approximately one order of magnitude, in comparison to the result of the planar MOS capacitors on the (0001) face under the same NO annealing condition. In addition, it is found that Fowler–Nordheim tunneling current occurs at an oxide electric field of 7 MV/cm for the planar MOS device. However, Poole–Frenkel conduction current occurs at a lower electric field of 4 MV/cm for the trench MOS capacitor. This is due to the local field crowded at the trench corner severely causing the electrons to be early captured at or emitted from the SiO2/SiC interface. These results provide a reference for an in-depth understanding of the mobility-limiting factors and long term reliability of the trench and planar SiO2/SiC interfaces.