Comparative Analysis on Fault Tolerant Techniques for Memory Cells in Wireless Sensor Devices

Abstract

As technology scales, Multiple Cell Upsets (MCUs) become more common and affect a larger number of cells in memories while reading data for biomedical application using wireless sensor networks. In order to protect memories against SEUs(Single Event Upset) as well as MCUs it is necessary to make use of advanced Error detecting and correcting codes that can correct more than one error per word. A sub-group of the low-density parity checks (LDPC) codes, which be-longs to the family of the Majority logic decoding which has been recently proposed for memory application and Difference set codes (DC) are one example of these codes which contributes for error detection and correction in the memories. (Majority Logic) ML decodable Codes are suitable for memory applications in Wireless Sensor Devices (WSD). In this paper, the similar investigation made for fault-detection and correction strategy which significantly makes area overhead negligible and to lessen the deciphering time through DC codes than the current procedure and it gives promising alternative for memory applications with less on-chip power utilization on the grounds that the downsides in the current strategies is their failure to amend multiple bit errors at the outputs has to be overcome if researchers opt for hybrid codes.