Comparative analysis of GALS clocking schemes

Abstract

Because of the increase in complexity of distributing a global clock over a single die, globally asynchronous and locally synchronous systems are becoming an efficient alternative technique to design distributed system-on-chip (SOC). A number of independently clocked synchronous domains can be integrated by clock pausing, clock stretching or data-driven clocking techniques. Such techniques are applied on point-to-point inter-domain communication schemes. Presented here is a comparison of these schemes and how they can be applied to an existing partitioned synchronous architecture to obtain a reliable, low-latency and efficient clock control architectures. The comparison highlights the advantages and disadvantages of one scheme over the other in terms of logical correctness, circuit implementation, performance and relative power consumption. Also presented are circuit solutions for stretchable and data-driven clocking schemes. These circuit solutions can be easily plugged into existing partitioned synchronous islands. To enable early evaluation of functional correctness, also proposed is the use of Petri net modelling techniques to model the asynchronous control blocks that constitute the interface between the synchronous islands.