Abstract
The ferroelectric field-effect transistor (FeFET) is one of the most promising candidates for emerging nonvolatile memory devices owing to its low write energy and high $I_{\mathrm {ON}}/I_{\mathrm {OFF}}$ ratio. For FeFET applications as nonvolatile memory devices, 1FeFET, 1T-1FeFET, 2T-1FeFET, and 3T-1FeFET cells have been proposed. The 1FeFET cell exhibits the highest density but suffers from write disturbance. Although the 1T-1FeFET and 2T-1FeFET cells resolve the write disturbance, they use a write scheme with a negative write voltage ( $V_{\mathrm {W}}$ ), which requires voltage swings of many control signals, leading to a significantly high write energy consumption. The 3T-1FeFET cell uses a write scheme without a negative $V_{\mathrm {W}}$ ; however, it exhibits the largest area overhead. Although the 1T-1FeFET cell resolves the write disturbance with a small area overhead; however, it exhibits high write energy consumption because of the use of a negative $V_{\mathrm {W}}$ . In this paper, to significantly reduce the write energy consumption, we propose a less control signal swing (LCSS) write scheme without using a negative $V_{\mathrm {W}}$ . Simulation results indicate that the worst, average, and best cases of the proposed LCSS write scheme can achieve 35%, 66%, and 96% lower write energy consumption, respectively, than the write scheme with a negative $V_{\mathrm {W}}$ in the 1T-1FeFET cell. We also identify the available sensing schemes for each FeFET cell in the read operation according to the FeFET threshold voltage distribution.
Highlights
In the past decades, static and dynamic random-access memory (SRAM and DRAM, respectively) have been conventionally used as cache and main memory, respectively
The 1T1FeFET cell can address the write disturbance; it uses a write scheme with a negative VW, which incurs high write energy consumption
The 2T-1FeFET cell can control the read current during the read operation; it uses a write scheme with a negative VW
Summary
Static and dynamic random-access memory (SRAM and DRAM, respectively) have been conventionally used as cache and main memory, respectively. These memory devices face the following challenges Because they use a current-based write scheme, a high write current flows during the write operation, which causes high write energy consumption [12]. The 1T-1FeFET and 2T-1FeFET cells use a write scheme with a negative write voltage (VW) This causes increased control signal swing to prevent write disturbance in unselected rows. Because the 3T-1FeFET cell uses a write scheme without a negative VW, it exhibits a lower write energy consumption Both current- and voltage-based sensing schemes can be used regardless of the VTH distribution. The analyzed 1T-1FeFET cell solves the write disturbance problem and exhibits a small area overhead It exhibits a high write energy consumption because it uses a negative VW.
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