Compact, Programmable, Two-Stage Configuration for Implantable Biopotential Recording Amplifiers

Abstract

This paper proposes an area-efficient CMOS amplifier for neural recording applications. The proposed neural amplifier takes advantage of indirect negative feedback to realize a rather low upper [Formula: see text]3-dB cutoff frequency. As a result, the capacitance needed to realize the cutoff frequency is so small that can be easily implemented on-chip. Moreover, the proposed circuit also employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. Designed based on a two-stage configuration, the amplifier provides tunable lower cutoff frequency and digitally-programmable upper cutoff frequency and voltage gain. The circuit is designed in a 0.18-[Formula: see text]m technology, and consumes 0.022[Formula: see text]mm2 and 0.27[Formula: see text]mm2 of chip areas for single- and eight-channel designs, respectively. Operated with a supply voltage of 1.8[Formula: see text]V, power consumption of the proposed amplifier is 36.7[Formula: see text][Formula: see text]W with the simulated input-referred noise of 4[Formula: see text][Formula: see text] over 1[Formula: see text]Hz–10[Formula: see text]kHz for each channel. The amplifier also provides an output swing of 0.95 Vpp with a total harmonic distortion of [Formula: see text]50[Formula: see text]dB at the frequency of 1[Formula: see text]kHz.