Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology

Abstract

For RRAM to be a cost-competitive candidate for high-density and high-capacity commercial products, some architectural-level challenges must be tackled. In this paper, research results that advance the design of high-density RRAM arrays are presented. We first focus on the scaling effects of on-chip interconnects on RRAM array performance. Due to the continuously shrinking process feature size, the voltage drop along the interconnect gradually reduces the voltage available to operate the RRAM device. To more efficiently analyze this effect for an arbitrary array size, a compact array model is developed. Simulations using this model determine the maximum achievable array size for future technology nodes. A compact, one-transistor-N-RRAM (1TNR) array architecture, with corresponding read/write and decoding schemes, that achieves high RRAM density is then introduced. A proof-of-concept 1T4R test chip with fully integrated RRAM devices is described. For this test chip, a particular sequence to form the cross-point RRAM array is presented. Measurement results of successful array operations demonstrate the feasibility and reliability of the proposed high-density architecture.