Compact nonlinear thermal networks for accurate modeling of smart power ICs

Abstract

Most power semiconductors are subject to substantial self-heating, especially in case of failure conditions such as a shorted load. Therefore, temperature sensors are usually integrated to allow safe turn-off, thus avoiding device destruction, and advanced concepts with multiple sensors, some far away from the heat source, are receiving increased attention. To investigate and optimize the behavior of such designs, system simulations are required that accurately take the thermal coupling between the power device and the temperature sensors into account. For this purpose we present a method for the derivation of nonlinear thermal networks that correctly model the thermal behavior and coupling of on-chip devices. They can easily be included in standard circuit and system simulators and are comparatively simple so that simulation time is not increased significantly. Nevertheless, these networks take all relevant thermal resistances and capacitances of the chip, package, and mounting into account. Moreover, they are accurate even for large temperature swings since they consider the temperature-dependent behavior of silicon. Our approach will be demonstrated for a typical smart power IC and validated by comparison to measurement results.