Abstract
This letter reports on compact models of voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IR</i> ) drops in a power delivery network (PDN) for through-silicon-via-based 3-D integration and packaging. The 3-D PDN is modeled with SPICE to investigate the dc voltage distribution in 3-D chip stacks. Analytical formulas are derived for estimating voltage drops for two typical types of vertical interconnect arrangements: uniform and peripheral distributions. With good agreements, analytical calculations reveal that the voltage drop has a quadratic correlation with the number of chips in a stack. The compact models provide important insights of 3-D PDNs for 3-D system design.
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