Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors

Abstract

In this paper, a compact SPICE model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs) is developed with considering effects when scaling the transistor size down to the 10-nm technology node. The model supports different transistor design parameters such as width, length, oxide thickness, and various channel materials, as well as the applied strain , which enables the evaluation of transistor- and circuit-level behavior under process variation and different levels of bending. Extensive device-level simulations are performed using this model, and TMDFETs are compared with different Si- and graphene-based devices. We performed circuit-level simulations, and reported the delay, power, and EDP of the benchmark circuits. Effects from process variation are also evaluated. These cross-technology studies show that TMDFET’s power is comparable to the low-power multigate devices (about 0.4% lower). The delay and EDP are 60% and 2.3% higher than the graphene-based devices, respectively. The developed compact model would enable SPICE-level circuit simulation for early assessment, design, and evaluation of futuristic TMDFET-based flexible circuits targeting advanced technology nodes.