Compact modeling of memristive IMP gates for reliable stateful logic design

Abstract

Introducing non-volatility into CMOS circuits is a promising solution to overcome the standby power dissipation due to leakage, which has become a major challenge of today's VLSI. Stateful logic inherently realizes non-volatile logic-in-memory circuits with zero-standby power and opens the door for a shift away from the Von Neumann architecture. To ensure a correct logic behavior in all input patterns, the reliability of the conditional switching in the stateful logic gates is the most important design objective. In this work the goal is to efficiently calculate the reliabilities in TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based and spintronic stateful implication (IMP) logic gates with the aid of compact but sufficiently accurate device models. It is demonstrated that in order to avoid a state computation error in the TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based IMP gate, refreshing is required after a limited number of logic steps as the state drift errors accumulate. Due to the magnetic bistability of the magnetic tunnel junctions (MTJ), spin-transfer torque (STT)-MTJ-based IMP logic gates eliminate error accumulation and thus are inherently suited for digital computing. A modified SPICE model is presented to optimize the circuit parameters of the STT-MTJ-based gates for providing a reliable conditional switching behavior.