Compact Hardware Implementation of the Block Cipher Camellia with Concurrent Error Detection

Abstract

A compact hardware implementation of a block cipher is attractive for any low-cost embedded application like smart cards. In this paper, a compact hardware architecture for Camellia is investigated. In this architecture, encryption and key scheduling share the same datapath and a four s-box iterative structure is employed. In the hardware design of cryptographic algorithms, concurrent error detection (CED) techniques have been proposed not only to protect the encryption and decryption process from random faults but also from the intentionally injected faults by some attackers. In our design, we also investigate a multiple parity code based error detection scheme. In our CED scheme, all the components are protected and all single-bit faults and most multiple faults will be detected. We study the implementation of the compact architecture for an ASIC and an FPGA. The design requires 14.12K gates with a throughput of 143 Mbps based on 0.18-um CMOS standard cell library and 1052 slices with a throughput of 135 Mbps based on Xilinx Virtex-E v1000efg860 chip. For our concurrent error detection, the hardware overhead is about 83%.