Abstract
This letter presents a methodology for the design of high-performance miniaturized Circular Power Dividers (CPDs) for wideband applications. To accomplish this objective, annular slots are strategically incorporated into patch and the ground plane of CPDs. This, in turn, increases the effective path length of the surface current flowing across the patch. This yields miniaturization, improved impedance matching, reduced insertion loss and increased isolation over a larger bandwidth. A mathematical model is developed for the design of the proposed configuration called Circular power dividers with Defected Ground Plane(CDGP). The presented model has been verified through various simulations and practical measurements. By implementing this approach, a substantial miniaturization of approximately 83% and more than threefold increase in bandwidth has been achieved when compared with non-slotted CPDs. Moreover, there is improvement in insertion loss, isolation, and return loss as well. There is good agreement between the mathematical model, simulation results and measured parameters.
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