Compact and fast multiplier using dual array tree structure

Abstract

A parallel multiplier topology with compact area and fast speed is presented. This new architecture includes dual partial product arrays, which are divided from one partial product plane of a conventional array multiplier. Due to parallel operation of this proposed dual array, multiplication speed is increased twice. Outputs of both arrays are summed with a binary tree adder, while each partial product array is made with full adders. This proposed multiplier fabricated in a 1.0-/spl mu/m double metal CMOS process, operates at 16 nSec in the worst case of 70/spl deg/C and 4.75 volt power voltage. >