Compact and efficient structure of 8-bit S-box for lightweight cryptography

Abstract

In this paper, we design an inversion-based S-box with better hardware implementation than the AES S-box with similar cryptographic properties. The proposed S-box computation involves basically two steps, the field inversion, and the affine transformation. The constructed S-box uses a cost-efficient affine transformation with low area resources and low critical path delay (CPD). The sub-blocks of the S-box, such as field inversion in F24, are implemented based on the efficient circuits. A large number of gates, in the structure, have been implemented by 2-input NAND and 2-input NOR gates to reduce delay and area. The cryptographic strength of the proposed S-boxes is analyzed by studying the properties of S-box such as Nonlinearity, Differential uniformity (DU), Strict avalanche criterion (SAC), Algebraic degree (AD), Differential approximation probability (DAP), and Linear approximation probability (LAP) in SAGE. Security analysis of the proposed S-box shown that the structure has the security level equal to the AES S-box. Therefore, this structure can be used in the lightweight block ciphers. Also, the implementation results, in 180 nm and 65 nm CMOS technologies, show the proposed S-box is comparable in terms of area, delay, and area×delay than most of the famous S-boxes.