Abstract
In this paper, we argue that communication at the speed of light (CaSoL) through on-chip copper interconnects is possible in the near future based on giga-scale integration (GSI) technologies. A three-step algorithm is introduced to design the optimum buffers in such systems. HSPICE simulations show that a $1.3\times $ time of flight ( ${T}_{\text {F}}$ ) is reachable in 7-nm FinFET technology. It is also shown that such a design is by nature, robust, and immune to process variations and crosstalk noise.
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