Common Mode Noise Reduction of Three-Level Active Neutral Point Clamped Inverters With Uncertain Parasitic Capacitance of Photovoltaic Panels

Abstract

SiC devices can upgrade the inverter performance to a new level by its potentially more than ten times higher switching speed compared to its Si counterpart. However, the high switching frequency and dv/dt, di/dt worsen the electromagnetic interference. Reduction of the common mode (CM) noise of the non-isolated photovoltaic (PV) inverters is addressed by many researchers through adding filters or balancing the circuit. However, most methods rely on the certainty of the parasitics in the system in advance. It is usually not practical for a PV inverter because the parasitic capacitance of PV panels that are to be installed in plants varies from case to case and further can be seriously affected by the damp environment. This article proposes a practical way to reduce the CM noise of the three-level active neutral point clamped (ANPC) inverters with uncertain parasitic capacitance of PV panels. First, the CM model of ANPC inverters with all parasitic capacitances is established. Next, most existing hardware-based reduction methods of the CM noise are summarized based on a unified mathematical model and further compared with each other. After the comparison, a practical method is proposed to reduce the CM noise of the ANPC inverter with uncertain parasitic capacitances, which just adds little volume and cost to the whole system. Finally, the simulation and experiments are conducted to validate the proposed method.