Combining Error Control Codes with Crosstalk Reduction

Abstract

Conventional error control codes (ECCs) has been successfully applied to improve the reliability of on-chip interconnect by correcting logic errors. Unfortunately, ECCs is inefficient to address crosstalk-induced delay uncertainty, which greatly decreases the system performance even causing timing errors. Crosstalk-induced delay uncertainty results from the dependence of coupling capacitance and inductance on different wire switching patterns. In this chapter, we mainly focus on the delay uncertainty caused by the capacitive crosstalk coupling. The capacitive crosstalk induced delay uncertainty can be alleviated by techniques such as shielding, routing, wire sizing and spacing, crosstalk avoidance codes (CACs), skewed transitions, and staggered repeater. Typically, these methods do not address logic errors. In this chapter, we will discuss the solutions, which efficiently address both logic errors and capacitive crosstalk induced delay uncertainty simultaneously.