Abstract

AbstractSilicon nanocrystals (Si‐ncs) embedded in a dielectric matrix (e.g. Si3N4, SiO2) attract significant interest for their use in silicon‐based devices such as memories, light amplifiers, and light emitting diodes. Si‐ncs in an SiO2 matrix are generally obtained through thermal annealing of silicon‐rich oxide (SRO) at elevated temperatures (900–1200 °C). In this study, we have investigated the composition of annealed SRO layers close to the interfaces with Si3N4, or c‐Si with XPS, SIMS, and atomic force microscopy (AFM). The analyses indicate an approximately 2‐nm thick Si‐depleted region close to both the Si3N4 and c‐Si interface formed after annealing at 1050 °C. The formation of this Si‐depleted layer is of importance for both electrical transport and charge storage in annealed SRO. Copyright © 2008 John Wiley & Sons, Ltd.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call