Combined DEVS multiresolution simulation and model checking

Abstract

We propose using Multiresolution Modeling (MRM) for system level design of networked software systems. This methodology aids in creating a family of models at different levels of complexity. We have developed an MRM framework to support hierarchical modeling as exemplified for Network-on-Chip (NoC) systems, as exemplar of network systems, with support for both validation and verification. Throughout the design phase, fine-grain models are created using their coarse-grain counterparts. Each model can be validated using discrete-event simulation and verified using model checking. We propose Constrained-DEVS, a variant of the Discrete Event System Specification (DEVS) formalism, which supports model checking in addition to DEVS's discrete-event simulation capability. Appropriate execution protocols for mixed V&V (validation and verification) are proposed. This leads to an MRM framework enabling both simulation and model checking. This framework is realized through extending the DEVS-Suite simulator and its applicability demonstrated for exemplar NoC models.