Combinatorial Multi-Objective Optimization of SFCL and SMES for the Low-Voltage Ride-Through Fulfillment of Solid-State Transformer

Abstract

To figure out the low-voltage ride-through (LVRT) problem of a solid-state transformer (SST), this paper proposes a methodology that combinatorically optimizes a resistive superconducting fault current limiter (SFCL) and a superconducting magnetic energy storage (SMES) unit. The goal of minimizing the capacities of the resistive SFCL and the SMES while achieving the LVRT of the SST is designed, and a multi-objective Pareto optimization is carried out. Firstly, the modeling of a three-stage SST with a resistive SFCL and a SMES is presented through theoretical analysis, and the SST's fault transient characteristics are analyzed. Then, the optimization scheme based on the improved non-dominated sorting genetic algorithm-II (NSGA-II) is elaborated. The proposed approach is verified in a typical SST connecting a 10 kV power distribution network and a 380 V electricity grid. Using MATLAB/Simulink and RT-lab real-time simulation platform, different tests are done to check the rationality of the optimal solutions. The results reveal that a satisfying LVRT for the SST is guaranteed while minimizing the ratings of the SFCL and the SMES, and getting a proper reactive current injection. Consequently, the validity and suitableness of the proposed approach are well confirmed.